The field of the present invention relates generally to microdevices and microstructures, and more particularly to microfabrication processes to create micromechanical or microelectromechanical devices with integral electrical isolation structures within the devices.
Microelectromechanical systems (MEMS) refers to a technology in which electrical and mechanical devices are fabricated at substantially microscopic dimensions utilizing techniques well known in the manufacture of integrated circuits. Present commercial applications of MEMS technology are predominantly in pressure and inertial sensing, with an emphasis on automotive applications thereof. For an introduction to the use of MEMS technology for sensors and actuators, see for example the article by Bryzek et al. in IEEE Spectrum, May 1994, pp. 20-31.
The fabrication processes for MEMS, called micromachining, are borrowed from the integrated circuit industry, where semiconductor devices are fabricated using a sequence of patterning, deposition, and etch steps. Surface micromachining has typically used a deposited layer of polysilicon as the structural micromechanical material. The polysilicon is deposited over a sacrificial layer onto a substrate, typically silicon, and when the sacrificial layer is removed the polysilicon remains free standing. Bulk micromachining techniques, rather than using deposited layers on a silicon substrate, etch directly into the silicon wafer to make mechanical structures of the single crystal silicon itself. Bulk micromachining was first practiced using anisotropic wet chemical etchants such as potassium hydroxide, which etch faster in certain crystallographic planes of silicon. However, advancements in reactive ion etching (RIE) technology have made practical, and in many ways preferential, the use of dry plasma etching to define micromechanical structures. Reactive ion etching techniques are independent of crystal orientation, and can create devices exceeding the functionality of surface micromachined devices. The use of single-crystal materials, particularly silicon, can be beneficial for mechanical applications because of the lack of defects and grain boundaries, maintaining excellent structural properties even as the size of the device shrinks.
Deep reactive ion etching techniques developed specifically for the MEMS industry have enabled a greater range of functionality for bulk micromachining. Processes such as those described in U.S. Pat. No. 5,501,893 are now supplied by commercial etch vendors specifically for bulk micromachining. These processes provide silicon etch rates in excess of 2 um/min with vertical profiles and selectivity to photoresist greater than 50:1 or selectivity to silicon oxide greater than 100:1. This enables bulk micromachined structures to span the range from several microns deep to essentially the thickness of an entire wafer ( greater than 300 um).
The predominant difficulty in bulk micromachining is the requirement for most devices that the silicon of the microstructure be mechanically connected to but electrically isolated from the substrate silicon. In particular, if the device is electrically activated or transduced, the current path from the structure to the substrate must be reduced or effectively eliminated in order that the device function appropriately. This requirement has proven to be the most difficult to achieve in fabrication.
An example of a process for bulk micromachined structures is described in U.S. Pat. No. 5,719,073 which is assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference. This process uses a single mask layer and appropriate etch and deposition steps to create a fully self-aligned, metalized bulk micromachined structure. Reactive ion etching is used to define and undercut an array of cantilever beams, which are connected together in order to form a more complete functional microstructure. All structure elements and interconnects are formed with the same masking layer, and isotropic dry etch techniques are used to release the structural layer. The advantages of the process are the simplicity of the single masking layer, the reactive ion etch release process, the self-aligned metalization, and high manufacturing yield.
The process flow for the ""073 patent defines a pattern in a dielectric mask which is transferred to the single crystal material substrate by a 10-20 um trench etch. After the sidewalls of the trench are protected using a second dielectric layer, such as silicon dioxide, the silicon islands or mesas are undercut and released using an isotropic reactive ion etch. The released silicon mesas essentially become the cantilever beams. A final self-aligned metal layer is deposited onto the oxide layer on the beams, allowing electrical connection to the structure. The process of the ""073 patent can be carried out on a wafer having existing integrated circuitry, in which case the individual process steps are all performed at a temperature of less than 300xc2x0 C.
With the self-aligned metal layer of the ""073 patent, only one electrical connection is made to the microstructure. In situations where several connections are necessary, additional photolithography or masking steps must be performed on the released structure. These additional steps limit device yield, since photoresist application on and removal from a released microstructure often results in device failure. Although the metal layer of the ""073 patent is self-aligned, it has been found that evaporation or sputtering of metal on the sidewalls of 10-20 um deep beams is a difficult, non-standard process step, and the resulting metal layer is often highly nonuniform in thickness and will coat only a portion of the total beam depth. Further, metal-oxide-silicon interface is a source of parasitic capacitance for those devices which rely on opposing metal layers for capacitive actuation and transduction and the large area provided by the beam sidewalls in the ""073 patent and the metal-oxide-silicon beam structure directly results in a large parasitic capacitance. For many inertial sensing devices, the variable capacitance provided by opposing beam sidewalls is actually exceeded by the parasitic capacitance to the substrate silicon.
An attempt to modify the process of the ""073 patent to reduce the level of parasitic capacitance, and thus improve the device performance resulted in the invention described in U.S. Pat. No. 5,426,070, also assigned to the assignee of the present invention. Here, an oxidation step is carried out to consume sections of the silicon beams, converting these sections completely to oxidized segments. As a result, the remaining silicon of the microstructure is electrically isolated from the substrate silicon by an oxide beam segment. However, the thick oxide layer required for the insulating segment is also grown on sidewall surfaces of the surviving silicon beams, drastically modifying the mechanical performance of the composite beams. In addition, the self-aligned metalization creates only one contact to the microstructure and since the metal is required to coat the sidewalls of the beams, the result is the non-uniform and unreliable metal coverage described above.
Other techniques for providing isolation and parasitic capacitance reduction for bulk micromachined devices have been attempted. Many have relied on the use of specially prepared substrates such as silicon-on-insulator, where the wafer has a built-in buried oxide layer. The microstructure is formed from the silicon layer existing on the top of the buried layer, and released using chemical etching of the buried layer. However, the chemical etch to release the silicon microstructure has relatively low yield, and the substrate itself is specialized and expensive. In Brosnihan, et al., xe2x80x9cEmbedded interconnect and electrical isolation for high-aspect-ratio, SOI inertial instruments,xe2x80x9d Transducers 97, pp. 637-640, the authors combine the SOI substrate with nitride and polysilicon isolation blocks. However, the structure definition and release still depend on the buried SOI layer and the resulting expensive substrate preparation.
As bulk micromachined devices increase in complexity it becomes increasingly important to improve their electrical performance. Multiple electrical connections are required for more complex MEMS. devices. Electrical isolation between the various connections, and between the structure and the substrate, are also required. Typically such isolation is accomplished in the prior art by separating conducting metal layers by insulating dielectric layers. See for example U.S. Pat. No. 5,611,940. It is also well known in the prior art to provide dielectric isolation regions between microelectronic devices or conductors in integrated circuits, as in U.S. Pat. Nos. 4,688,069 and 4,876,217. A particularly beneficial approach to electrical isolation has been the use of trenches filled with insulating material, described in U.S. Pat. Nos. 4,104,086, 4,509,249, 4,571,819, and 4,519,128. Although the electrical isolation schemes in the prior art are very satisfactory for conventional integrated circuit devices, they have serious shortcomings when applied to microelectromechanical devices.
MEMS devices contain moving mechanical microstructures, typically exhibiting substantially three-dimensional geometries. The existence of these structures precludes, or makes very difficult, the application of electrical isolation schemes such as those described in the prior art. Such schemes involve multiple steps of lithography, etching, and deposition. These steps are not feasible on structures exhibiting large topographic variations, nor on microstructures which have been previously released for motion.
What is required for effective electrical isolation in MEMS devices is a new electrical isolation process which must be compatible with the specific requirements and limitation of MEMS devices, most notably the existence of released, movable microstructures.
What is also required of the electrical isolation process is that it provide isolation between adjacent mechanical structures, between different electrical segments, and between the device and the substrate material. In bulk micromachining, this most often means breaking the electrical continuity between the structure silicon and the substrate silicon. It is desired that such an isolation structure should also provide for reduced parasitic capacitance in the device. MEMS sensors typically require the ability the measure very small changes in electrical charge or capacitance, and therefore must minimize the effect of parasitic circuit elements.
Further what is needed is an electrical isolation process which does not have an adverse impact on the manufacturing yield of MEMS devices. The commercial viability of MEMS technology depends on cost effective manufacturing of products. Prior art electrical isolation schemes may result in very low manufacturing yields and hence unacceptably high costs for most MEMS product applications.
In order to achieve the foregoing and to overcome the problems inherent in prior electrical isolation schemes, the present invention is directed to a beam-level isolation technique in which insulating segments are incorporated within silicon beam microstructures to provide electrical isolation.
It is therefore an object of the present invention to provide suitably modified trench isolation techniques, utilizing dielectric materials, in conjunction with micromechanical device fabrication processes to achieve electrical isolation within the microstructure.
It is a further object of the invention to eliminate the use of unsuitable and unreliable sidewall metal layers for electrical activation of a MEMS device, and instead to use the silicon cores of microstructure beams for conduction and as capacitor plates. This is achieved by creating contacts from a metal layer through a dielectric layer to the silicon beams using techniques which are common in the art.
It is a further object of the invention to provide multiple metal interconnections within a MEMS device. This is achieved by placing metal conductor lines over isolation segments and on top of cantilever beams to provide multiple metal paths. The conductor lines are separated from the core silicon by an insulating layer which is also present on top of the beams, thus achieving isolation between the metal and the silicon.
It is a further object of the invention to alleviate dielectric-induced stress on silicon beam microstructures by minimizing the amount of sidewall film present on the silicon. Thermal oxidation of existing beam structures creates a thick sidewall oxide film which dominates device characteristics. By performing isolation processes before structure formation, sidewall films can be reduced or even eliminated, and hence passivation films can be rendered unimportant to device performance.
It is a further object of the invention to provide a trench isolation process for fabricating microstructures which is scalable to different structure etch depths, while maintaining high manufacturing yield. The trench isolation process may be scaled to etch depths greater than 50 um using deep reactive ion etching techniques, and can be adjusted to a particular microstructure depth. Planar lithography for the isolation segments, metal deposition, and structure definition maintains high manufacturing yield and does not deviate from techniques common to the semiconductor processing industry.
Although the preferred embodiment of the invention is to use thermal oxidation to form the isolation segments, other lower temperature chemical vapor deposition techniques can also be used for trench isolation. Further, even with high temperature oxidation steps, it is possible to integrate the micromechanical isolation process with integrated circuits without significant interleaving of the process steps.
Briefly, the basic process begins by defining an isolation trench pattern for a desired micromechanical structure on an oxide coated silicon wafer. The pattern defines the region, or regions, where dielectric isolation segments will be placed. These dielectric segments serve to separate the silicon of the micromechanical structure from the silicon of the substrate. The pattern for the dielectric segments present in the exposed photoresist is transferred to the oxide underlayer using a reactive ion etch. Then, an isolation trench is defined in the wafer using silicon reactive ion etching, typically 1-1.5 um wide and 10-50 um deep into the substrate silicon. The shape of the trench, or the trench profile, is optimized to improve the isolation properties of the segment in conjunction with the remainder of the microstructure processing steps. In the preferred embodiment, the trench profile is reentrant, with a wider width at the bottom of the trench than at the top of the trench. The purpose of shaping the trench is to reduce the possibility of silicon filaments forming during the remainder of the processing. Such filaments may surround the isolation segment and provide a leakage path which reduces the efficacy of the isolation.
After the isolation trench is defined, the trench is filled with a dielectric, preferably with a thermal oxidation step. Alternatively, the trench may be filled using chemical vapor deposition techniques with silicon dioxide or silicon nitride. During thermal oxidation, the silicon sidewalls of the trench are consumed to form silicon dioxide, and the resulting volumetric expansion narrows the trench opening to effectively fill the trench. Because of the high aspect ratio of the trench, a void is often formed within the dielectric. Unlike most electrical isolation schemes, however, the void is unimportant to device operation.
After the trench is filled, the wafer surface has small topography variations around the locations of the isolation segments. Therefore, a planarization step is performed, normally with photoresist, to smooth the surface of the wafer and prepare it for the patterning and deposition steps to follow. An application of resist or other viscous material, and subsequent etchback, is used to planarize the small nonuniformities in the surface and reduce the thickness of the dielectric on the surface of the wafer.
Next, a second masking layer defines vias in locations where connection is to be made from a subsequent metal layer to the silicon beam structures or the silicon substrate. Eventually, metal to silicon contacts are made through the vias as is typical of integrated circuit processing. The via pattern in the photoresist is transferred to the silicon oxide using RIE processes, and the silicon surface is exposed for contact processing. After implantation and annealing of dopants, the metal layer is sputter deposited. The metal layer forms the contacts to the underlying silicon and is also used, in conjunction with further processing, to create multiple interconnections to the micromechanical device.
A third photolithography step coarsely patterns the metal in preparation for the final structure etches. The coarse metal pattern is transferred to the metal layer using a wet chemical etch step or a dry reactive ion etch. The coarse metal patterning step removes metal from the regions where the interconnections are to be broken. A final lithographic patterning step defines the micromechanical structure in the form of an interconnected grid of silicon beams. The beams are created by transferring the photoresist pattern through the metal and dielectric masking layers. Silicon islands or mesas are defined using a silicon trench etch which surrounds the mesa features. After the sidewalls of the beams are passivated using a dielectric layer, the beam features are released using an isotropic reactive ion etch. The sidewall passivation layers can be removed, if desired, by another isotropic reactive ion etch, etching dielectric preferentially to silicon.
In summary, the process of this invention creates a silicon structure similar to those developed in the ""703 patent, but offering several substantial advantages. A metal conductive layer is present on the top of the beam structures only. Isolation segments are incorporated into the silicon beams, reducing parasitic capacitance and providing multiple structure connections. In regions where capacitive actuation or sensing is required, the metal layer contacts the beam silicon cores, which serve as the capacitor plates. This is allowed because the isolation segments interrupt the conduction path from the silicon beams to the substrate silicon. Multiple conduction paths are possible using the top conductive metal layers and the contacts to the underlying silicon. The process is greatly improved from the prior art because a sidewall metal layer is not required, and multiple connections to the released microstructure are possible. The process is inherently manufacturable because all photolithography steps are performed on a flat surface, and none are performed on a released structure. The process can be merged with integrated circuits to create fully integrated systems on a chip.